A ferroelectric memory (FeRAM) stores information by using the hysteresis characteristics of a ferroelectric material. In the ferroelectric memory, a ferroelectric capacitor having a ferroelectric film as a capacitor dielectric film between a pair of electrodes is formed in each memory cell. In a ferroelectric material, polarization occurs in accordance with the applied voltage between the electrodes, and spontaneous polarization remains even after the applied voltage is removed. Also, when the polarization of the applied voltage is inverted, the polarization of the spontaneous polarization is also inverted. Therefore, information can be read out by detecting the spontaneous polarization.
As in other semiconductor devices, it is necessary to reduce the cell area in the ferroelectric memory as well. The structures of the ferroelectric memory are roughly classified into a planar structure and a stack structure, and the cell area of the stack structure is smaller than that of the planar structure. In the stack structure, a capacitor is formed immediately on a plug which is formed on a drain of a field-effect transistor formed in each cell. That is, a barrier metal film, a bottom electrode, a ferroelectric film, and a top electrode are sequentially deposited immediately on a W plug.
The barrier metal film suppresses diffusion of oxygen from the upper layer to the W plug. As the material of the barrier metal film, a combination of TiN, Ir, IrO2, Pt, and SRO (SrRuO3) is used. Since, however, many materials of the barrier metal film can also function as the bottom electrode, it is impossible to clearly distinguish between the barrier metal film and the bottom electrode. An example of a structure combining the barrier metal film and the bottom electrode film is a structure in which an Ir film, a IrO2 film, a Pt film, a PtO film, and a Pt film are sequentially stacked.
To meet demands on micropatterning of devices, it is favorable to etch the side surfaces of the films composing the capacitor into a substantially vertical shape having no slope. Examples of etching are a method of simultaneously etching these films, and a method of simultaneously etching the top electrode film and the ferroelectric film.
To form a ferroelectric capacitor having the stack structure by using simultaneous etching, etching using a hard mask is necessary. This is so because the selectivity between an organic resist mask and the ferroelectric film is low.
SiO2, SiN, TiN, and the like are extensively used as the materials of the hard mask used in simultaneous etching. Of these materials, TiN is suited as an etching mask material for forming the ferroelectric capacitor, since TiN is hardly etched during etching using a gas formed by adding oxygen to halogen.
Unfortunately, in etching using a gas formed by adding oxygen to halogen, the etching rate significantly lowers when the ferroelectric film is etched. Therefore, the use of the gas as described above during etching of the ferroelectric film is unpreferable in respect of the throughput.
By contrast, the throughput increases when a hard mask having a layered structure in which an SiO2 film is formed on a TiN film is formed, the SiO2 film is used as a mask until the ferroelectric film is etched, and the TiN film is used as a mask when the bottom electrode film is etched.
Note that after the films forming the ferroelectric capacitor are deposited, the back surface (lower surface) of the wafer must be cleaned in order to remove the residue of the organic resist used when a contact hole and the like are formed.
Although the throughput increases when simultaneous etching using the hard mask having the layered structure as described above is performed, during the formation of TEOS (TetraEthylOrthoSilicate) film, peeling may occur between the top electrode film and hard mask over the entire surface of the wafer, or may occur in the bottom electrode film and barrier metal film on the edge of the wafer.
Also, omission of the capacitor may occur when simultaneous etching is performed or the hard mask is removed. That is, the top electrode, the capacitor dielectric film, and the like composing the capacitor sometimes completely disappears by peeling.
On the other hand, Japanese Patent Laid-Open No. 2001-135798 discloses a structure which uses a metal silicide layer as a wiring layer in contact with the top electrode, in order to suppress deterioration of the characteristics of the ferroelectric capacitor caused by annealing after a metal interconnection is formed. In the structure, a layered material of an IrOx film and an Ir film is used as the top electrode. Also, in the fabrication of a capacitor element, the top electrode film is patterned using lithography (resist mask) and dry etching, and the ferroelectric film and the bottom electrode film are patterned using lithography and dry etching after that.
In the conventional fabrication method, however, no simultaneous etching of the top electrode film, the ferroelectric film, and the bottom electrode film is performed, so the hard mask is necessary if the simultaneous etching is performed. Accordingly, the method cannot solve the problem of peeling as described above.
Patent reference 1
Japanese Patent Laid-Open No. 2001-135798